Wednesday, July 19, 2017

core architecture

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guidance set
For more info in this topic, see % practise listings.
percent's commands range from about 35 instructions for the low-quit images to over 80 commands for the high-cease pics. The preparation set consists of instructions to carry out an expansion of operations on registers immediately, the accumulator and a literal consistent or the accumulator and a register, in addition to for conditional execution, and application branching.
some operations, which include bit putting and trying out, can be carried out on any numbered sign in, however bi-operand mathematics operations constantly contain W (the accumulator), writing the result again to both W or the alternative operand register. To load a regular, it's far necessary to load it into W before it could be moved into some other sign up. at the older cores, all sign in moves had to pass through W, but this modified at the "excessive-end" cores.

percent cores have pass instructions, which can be used for conditional execution and branching. The skip instructions are "skip if bit set" and "skip if bit no longer set". due to the fact cores before PIC18 had only unconditional department commands, conditional jumps are applied with the aid of a conditional skip (with the opposite situation) observed via an unconditional branch. Skips also are of software for conditional execution of any immediately single following guidance. it is feasible to skip bypass commands. for instance, the practise sequence "pass if A; pass if B; C" will execute C if A is genuine or if B is fake.

The 18 series implemented shadow, registers which keep numerous critical registers for the duration of an interrupt, providing hardware guide for robotically saving processor country while servicing interrupts.

In preferred, % commands fall into 5 training:

Operation on running register (WREG) with eight-bit instantaneous ("literal") operand. E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One education extraordinary to the percent is retlw, load instantaneous into WREG and return, that is used with computed branches to produce lookup tables.
Operation with WREG and indexed sign up. The result can be written to either the working register (e.g. addwf reg,w). or the selected sign up (e.g. addwf reg,f).
Bit operations. these take a sign up quantity and a chunk variety, and perform one of 4 actions: set or clean a piece, and test and pass on set/clean. The latter are used to carry out conditional branches. the same old ALU reputation flags are to be had in a numbered register so operations which includes "department on deliver clear" are viable.
control transfers. apart from the bypass commands formerly stated, there are most effective two: goto and make contact with.
a few miscellaneous zero-operand instructions, inclusive of return from subroutine, and sleep to go into low-energy mode.

overall performance

The architectural decisions are directed on the maximization of pace-to-fee ratio. The p.c structure changed into some of the first scalar CPU designs[citation needed] and continues to be some of the simplest and cheapest. The Harvard structure, wherein instructions and records come from separate sources, simplifies timing and microcircuit design significantly, and this advantages clock velocity, charge, and strength consumption.

The % preparation set is applicable to implementation of rapid research tables within the software space. Such lookups take one practise and two instruction cycles. Many capabilities can be modeled in this manner. Optimization is facilitated by way of the exceedingly large application area of the % (e.g. 4096 × 14-bit words at the 16F690) and by way of the design of the education set, which allows embedded constants. for instance, a branch education's target can be listed by way of W, and execute a "RETLW", which does because it is named – return with literal in W.

Interrupt latency is steady at three preparation cycles. external interrupts have to be synchronized with the four-clock education cycle, in any other case there can be a one preparation cycle jitter. inner interrupts are already synchronized. The constant interrupt latency lets in pics to reap interrupt-pushed low-jitter timing sequences. An example of this is a video sync pulse generator. this is not proper inside the newest percent models, due to the fact they have got a synchronous interrupt latency of three or four cycles.


Small education set to research
RISC structure
built-in oscillator with selectable speeds
easy entry degree, in-circuit programming plus in-circuit debugging PICkit devices to be had for much less than $50
cheaper microcontrollers
huge variety of interfaces which includes I²C, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet[24]
Availability of processors in DIL bundle lead them to easy to handle for interest use.


One accumulator
check in-financial institution switching is needed to get admission to the whole RAM of many gadgets
Operations and registers aren't orthogonal; some instructions can deal with RAM and/or instantaneous constants, at the same time as others can use the accumulator simplest.
the following stack boundaries had been addressed in the PIC18 collection, but nevertheless apply to earlier cores:

The hardware call stack is not addressable, so preemptive project switching cannot be implemented
software program-applied stacks aren't efficient, so it's far hard to generate reentrant code and guide neighborhood variables
With paged software reminiscence, there are two web page sizes to worry approximately: one for name and GOTO and any other for computed GOTO (commonly used for desk lookups). as an instance, on PIC16, name and GOTO have 11 bits of addressing, so the web page size is 2048 preparation phrases. For computed GOTOs, in which you add to PCL, the web page size is 256 instruction phrases. In both cases, the top cope with bits are provided by using the PCLATH sign up. This sign up should be changed each time manipulate transfers among pages. PCLATH must also be preserved by any interrupt handler.[25]

Compiler improvement

at the same time as several business compilers are to be had, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors.

As of 2013, Microchip gives their XC series of compilers, for use with MPLAB X. Microchip will subsequently phase out its older compilers, such as C18, and recommends the usage of their XC series compilers for brand spanking new designs.[26]

The clean-to-study RISC guidance set of the percent meeting language code could make the overall glide tough to comprehend. really appropriate use of simple macros can boom the readability of percent meeting language. for example, the unique Parallax p.c assembler ("SPASM") has macros, which conceal W and make the % appear like a -cope with gadget. It has macro commands like mov b, a (pass the data from address a to deal with b) and add b, a (upload information from deal with a to information in address b). It also hides the pass instructions through presenting three-operand department macro instructions, consisting of cjne a, b, dest (evaluate a with b and jump to dest if they're now not equal).

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