Wednesday, July 19, 2017

Device families leson 02

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PIC24 and dsPIC

For extra info on those households of microcontrollers, see % preparation listings § PIC24 and dsPIC sixteen-bit microcontrollers.
In 2001, Microchip brought the dsPIC collection of chips,[9] which entered mass production in past due 2004. they're Microchip's first inherently sixteen-bit microcontrollers. PIC24 gadgets are designed as fashionable motive microcontrollers. dsPIC devices consist of virtual signal processing skills further.

even though nevertheless similar to in advance percent architectures, there are substantial enhancements:[10]

All registers are 16 bits extensive
software counter is 22 bits (Bits 22:1; bit 0 is usually 0)
instructions are 24 bits extensive
data address area extended to 64 KiB
First 2 KiB is reserved for peripheral manage registers
information bank switching is not required except RAM exceeds 62 KiB
"f operand" direct addressing prolonged to 13 bits (8 KiB)
sixteen W registers available for sign up-check in operations.
(however operations on f operands always reference W0.)
instructions are available byte and (sixteen-bit) phrase paperwork
Stack is in RAM (with W15 as stack pointer); there is no hardware stack
W14 is the frame pointer
facts stored in ROM may be accessed immediately ("program area Visibility")
Vectored interrupts for different interrupt sources
a few features are:

(16×sixteen)-bit unmarried-cycle multiplication and other digital sign processing operations
hardware multiply–acquire (MAC)
hardware divide assist (19 cycles for 32/16-bit divide)
barrel moving
bit reversal
hardware guide for loop indexing
direct memory get admission to
dsPICs may be programmed in C the use of Microchip's XC16 compiler (formerly known as C30) which is a variant of GCC.

training ROM is 24 bits extensive. software program can access ROM in 16-bit words, where even words hold the least sizeable sixteen bits of each preparation, and strange words hold the maximum sizeable eight bits. The excessive half of ordinary phrases reads as 0. the program counter is 23 bits wide, but the least vast bit is continually 0, so there are 22 modifiable bits.

commands are available in  fundamental types, with most vital operations (add, xor, shifts, etc.) allowing both forms.

the primary is like the classic p.c instructions, with an operation among a exact f sign in (i.e. the primary 8K of RAM) and a unmarried accumulator W0, with a vacation spot pick bit selecting which is up to date with the end result. (The W registers are reminiscence-mapped. so the f operand may be any W register.)

the second one shape is more traditional, permitting three operands, which can be any of 16 W registers. The vacation spot and one of the assets additionally support addressing modes, allowing the operand to be in reminiscence pointed to by a W register.

PIC32M MIPS-based totally line[edit]
The PIC32M microcontrollers use the MIPS technologies M4K, a 32-bit MIPS32 processor.


In November 2007, Microchip introduced the PIC32MX circle of relatives of 32-bit microcontrollers, based at the MIPS32 M4K middle.[11] The tool can be programmed the use of the Microchip MPLAB C Compiler for PIC32 MCUs, a variant of the GCC compiler. the first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin well suited and proportion the same peripherals set with the PIC24FxxGA0xx circle of relatives of (sixteen-bit) gadgets permitting using not unusual libraries, software and hardware gear. these days, starting at 28 pin in small QFN packages up to excessive performance gadgets with Ethernet, CAN and USB OTG, complete family range of mid-range 32-bit microcontrollers are to be had.

The PIC32 structure added a variety of of latest capabilities to Microchip portfolio, consisting of:

the best execution speed 80 MIPS (120+[12] Dhrystone MIPS @ 80 MHz)
the biggest flash reminiscence: 512 kB
One instruction in keeping with clock cycle execution
the primary cached processor
allows execution from RAM
complete pace Host/dual position and OTG USB competencies
full JTAG and a couple of-wire programming and debugging
actual-time trace
In November 2013, Microchip added the PIC32MZ collection of microcontrollers, based on the MIPS M14K center. The PIC32MZ collection consist of:[13][14]

252 Mhz core speed, 415 DMIPS
Up to 2 MB Flash and 512KB RAM
New peripherals consisting of high-speed USB, crypto engine and sq.
In 2015, Microchip released the PIC32MZ EF family, the use of the up to date MIPS M5150 Warrior M-elegance processor.[15][16]

In 2017, Microchip added the PIC32MZ DA own family, presenting an included portraits Controller, photos Processor and 32MB of DDR2 DRAM.[17][18]


In June 2016, Microchip brought the PIC32MM own family, specialised for low-electricity and low-cost packages.[19] The PIC32MM features core-impartial peripherals, sleep modes right down to 500 nA, and 4 x four mm packages.[20]


Microchip brought the PIC32MK circle of relatives in 2017, specialized for motor control, business control, business net of factors (IIoT) and multi-channel CAN packages.

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